Driving connector and display device including the same

ABSTRACT

A display device includes a display panel and a driving connector connected to the display panel and from which driving signals are provided to the display panel, the driving connector including a driving integrated circuit, a gate pad through which a first driving signal is output from the driving connector to the display panel, a first input pad through which the first driving signal is input to the driving connector from outside thereof, and a gate driver which connects the gate pad to the first input pad and includes a first substrate and a transistor on the first substrate and including a source electrode connected to the first input pad and a drain electrode connected to the gate pad. Within the driving connector, the transistor and the driving integrated circuit are in order from the first substrate.

This application claims priority to Korean Patent Application No.10-2020-0134632, filed on Oct. 16, 2020, and all the benefits accruingtherefrom under 35 U.S.C. § 119, the contents of which are hereinincorporated by reference in their entireties.

BACKGROUND 1. Field

Embodiments relate to a display device. More particularly, embodimentsrelate to a display device having reduced bezel area.

2. Description of the Related Art

Display devices are used in various electronic devices such as smartphones, tablets, notebook computers and home appliances. The displaydevice may include a display area displaying an image and a non-displayarea (e.g., a bezel area) which surrounds the display area.

A plurality of pixels may be disposed in the display area. A pluralityof drivers may be disposed in the non-display area. The plurality ofdrivers (e.g., a data driver, a gate driver, etc.) may provide signalsto the pixels to display an image in the display area.

Research has been conducted to reduce an area in which the drivers aredisposed in order to enlarge the display area.

SUMMARY

Embodiments provide a display device having reduced bezel area.

In an embodiment, a display device includes a display panel including aplurality of pixels, and a driving module in which a first side is on anon-display area of the display panel, and including a drivingintegrated circuit, a gate pad, a first input pad and a gate driver. Thegate driver includes a first substrate and at least one transistor onthe first substrate and including a source electrode and a drainelectrode. The source electrode is connected to the first input pad, thedrain electrode is connected to the gate pad, and the driving integratedcircuit is on the transistor.

In an embodiment, the driving module may further include a firstconnection electrode and a second connection electrode on the transistorand a second input pad and a data pad on the first connection electrodeand the second electrode.

In an embodiment, the first connection electrode may connect the sourceelectrode and the first input pad, and the second connection electrodemay connect the drain electrode and the gate pad.

In an embodiment, the driving module may further include a firstmultiplexer connected to the data pad and a second multiplexer connectedto the gate pad.

In an embodiment, the first connection electrode may connect the secondinput pad and the driving integrated circuit, and the second connectionelectrode may connect the driving integrated circuit and the data pad.

In an embodiment, the driving module may further include a thirdconnection electrode between the first connection electrode and thesecond input pad and connecting the first connection electrode and thesecond input pad and a fourth connection electrode between the data padand the second connection electrode and connecting the data pad and thesecond connection electrode.

In an embodiment, the driving module may further include a firstconnection electrode and a second connection electrode on a same layeras the source electrode and a second input pad and a data pad on thefirst connection electrode and the second connection electrode.

In an embodiment, the first connection electrode may connect the secondinput pad and the driving integrated circuit, and the second connectionelectrode may connect the driving integrated circuit and the data pad.

In an embodiment, the driving module may further include a secondsubstrate between the transistor, and the first input pad and the gatepad.

In an embodiment, each of the first substrate and the second substratemay include polyimide.

In an embodiment, the driving integrated circuit and the gate driver mayoverlap.

In an embodiment, the driving module may further include a shieldingelectrode between the driving integrated circuit and the gate driver tooverlap the driving integrated circuit.

In an embodiment, the driving module may include a transmissive area atthe first side.

In an embodiment, the driving module may include at least one gateinsulating layer, at least one interlayer insulating layer and at leastone via insulating layer on the first substrate, and the at least onegate insulating layer, the at least one interlayer insulating layer andthe at least one via insulating layer may not overlap the transmissivearea.

In an embodiment, the display device may further include a circuit filmconnected to a second side opposite to the first side of the drivingmodule.

In an embodiment, the driving module may include a transmissive area atthe second side.

In an embodiment, the driving module may include at least one gateinsulating layer, at least one interlayer insulating layer and at leastone via insulating layer on the first substrate, and the at least onegate insulating layer, the at least one interlayer insulating layer andthe at least one via insulating layer may not overlap the transmissivearea.

In an embodiment, the driving module may include two or more drivingintegrated circuits.

In an embodiment, the gate driver may be connected to the drivingintegrated circuit.

In an embodiment, the driving module may include a plurality of groovesin the driving module at a second side and a third side which isperpendicular to the first side.

In an embodiment, a display device includes a display panel including aplurality of pixels, and a driving module in which a first side is on anon-display area of the display panel, and including a drivingintegrated circuit, a gate pad, a first input pad and a gate driver. Thegate driver includes a first substrate and at least one transistor onthe first substrate and including a source electrode and a drainelectrode. The source electrode is connected to the first input pad, thedrain electrode is connected to the gate pad, and the driving integratedcircuit is on the transistor.

Accordingly, the driving integrated circuit and the gate driver may besimultaneously in the driving module, and the bezel area of the displaydevice may be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the invention will becomemore apparent by describing in detailed embodiments thereof withreference to the accompanying drawings.

FIG. 1 is a plan view illustrating an embodiment of a display device.

FIG. 2 is a plan view illustrating an embodiment of a driving moduleincluded in the display device of FIG. 1.

FIG. 3 is a plan view illustrating an embodiment of a driving moduleincluded in the display device of FIG. 1.

FIG. 4 is a cross-sectional view illustrating an embodiment taken alongthe line I-I′ of FIG. 2.

FIG. 5 is a cross-sectional view illustrating an embodiment taken alongthe line I-I′ of FIG. 2.

FIG. 6 is a cross-sectional view illustrating an embodiment taken alongthe line I-I′ of FIG. 2.

FIG. 7 is a cross-sectional view illustrating an embodiment taken alongthe line I-I′ of FIG. 2.

FIG. 8 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2.

FIG. 9 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2.

FIG. 10 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2.

FIG. 11 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2.

FIG. 12 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2.

FIGS. 13 to 16 are cross-sectional views illustrating embodiments of thetransmissive area of FIG. 1.

FIG. 17 is a plan view illustrating an embodiment of a display device.

FIG. 18 is a cross-sectional view illustrating an embodiment taken alongline IV-IV′ of FIG. 17.

FIG. 19 is a cross-sectional view illustrating an embodiment taken alongline IV-IV′ of FIG. 17.

FIG. 20 is a plan view illustrating an embodiment of a driving moduleincluded in the display device of FIG. 1.

FIG. 21 is a plan view illustrating an embodiment of a driving moduleincluded in the display device of FIG. 1.

DETAILED DESCRIPTION

The invention now will be described more fully hereinafter withreference to the accompanying drawings, in which various embodiments areshown. This invention may, however, be embodied in many different forms,and should not be construed as limited to the embodiments set forthherein. Rather, these embodiments are provided so that this disclosurewill be thorough and complete, and will fully convey the scope of theinvention to those skilled in the art. Like reference numerals refer tolike elements throughout.

It will be understood that when an element is referred to as beingrelated to another element such as being “on” another element, it can bedirectly on the other element or intervening elements may be presenttherebetween. In contrast, when an element is referred to as beingrelated to another element such as being “directly on” another element,there are no intervening elements present.

It will be understood that, although the terms “first,” “second,”“third” etc. may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another element, component, region, layer orsection. Thus, “a first element,” “component,” “region,” “layer” or“section” discussed below could be termed a second element, component,region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. As used herein,“a”, “an,” “the,” and “at least one” do not denote a limitation ofquantity, and are intended to include both the singular and plural,unless the context clearly indicates otherwise. For example, “anelement” has the same meaning as “at least one element,” unless thecontext clearly indicates otherwise. “At least one” is not to beconstrued as limiting “a” or “an.” “Or” means “and/or.” As used herein,the term “and/or” includes any and all combinations of one or more ofthe associated listed items. It will be further understood that theterms “comprises” and/or “comprising,” or “includes” and/or “including”when used in this specification, specify the presence of statedfeatures, regions, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, regions, integers, steps, operations, elements,components, and/or groups thereof.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The term “lower,” cantherefore, encompasses both an orientation of “lower” and “upper,”depending on the particular orientation of the figure. Similarly, if thedevice in one of the figures is turned over, elements described as“below” or “beneath” other elements would then be oriented “above” theother elements. The terms “below” or “beneath” can, therefore, encompassboth an orientation of above and below.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to cross sectionillustrations that are schematic illustrations of idealized embodiments.As such, variations from the shapes of the illustrations as a result,for example, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments described herein should not be construed aslimited to the particular shapes of regions as illustrated herein butare to include deviations in shapes that result, for example, frommanufacturing. For example, a region illustrated or described as flatmay, typically, have rough and/or nonlinear features. Moreover, sharpangles that are illustrated may be rounded. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the precise shape of a region and are notintended to limit the scope of the present claims.

Hereinafter, the invention will be explained in detail with reference tothe accompanying drawings.

FIG. 1 is a plan view illustrating an embodiment of a display device.

Referring to FIG. 1, the display device may include a display panel DSP,a driving module DM and a circuit film CF. The driving module DM may beprovided in plural including a plurality of driving modules DM such astwo driving modules DM.

The display panel DSP may include a display area DA and a non-displayarea NDA which is adjacent to the display area DA. In an embodiment, thedisplay area DA is provided surrounding the display area DA. A pixel Pprovided in plural including plurality of pixels P may be disposed inthe display area DA. The pixels P may be generally disposed in thedisplay area DA. In an embodiment, for example, the pixels P may begenerally arranged in a matrix form in the display area DA. The pixels Pmay receive electrical signals such as a gate signal (e.g., a firstdriving signal among driving signals) and a data signal (e.g., a seconddriving signal among driving signals) from the driving module DM tocontrol the pixel P and display an image. One side of the driving moduleDM may be disposed on the non-display area NDA. Another side of thedriving module DM which is opposite to the one side may be connected tothe circuit film CF. The driving module DM may connect the display panelDSP to the circuit film CF. The circuit film CF may be an externaldevice from which an electrical signal is provided to the driving moduleDM.

In embodiments, the driving module DM may be bendable. In an embodiment,for example, the driving module DM which is bent may dispose the circuitfilm CF at a rear surface of the display panel DSP.

The circuit film CF may transmit the gate signal and the data signal tothe driving module DM. The driving module DM may provide the gate signaland the data signal from the circuit film CF to the pixels P.

In embodiments, a same one of the circuit film CF may be connected to aplurality of driving modules DM including two driving modules DM.However, this is exemplary, and a single one of the circuit film CF maybe connected to a single one of the driving module DM, or may beconnected to three or more of a plurality of driving modules DM. Inaddition, in embodiments, for convenience, it is illustrated in FIG. 1that the plurality of driving modules DM including six driving modulesDM are disposed on the display panel DSP, but this is exemplary and isnot limited thereto.

FIG. 2 is a plan view illustrating an embodiment of a driving module DMincluded in the display device of FIG. 1. FIG. 2 is a view illustratingan embodiment of a rear surface of the driving module DM illustrated inFIG. 1. FIG. 1 is a view of a front surface of the display panel DSP,the driving module DM and the circuit film CF, and each of thesecomponents includes a rear surface which is opposite to the frontsurface along a thickness direction of the display device.

Referring to FIGS. 1 and 2, a plurality of pads IP, GP and DP and adriving integrated circuit DIC may be disposed within the driving moduleDM. In embodiments, the plurality of pads may include a gate pad GP(e.g., first pad or first output pad) provided in plural including aplurality of gate pads GP, a data pad DP (e.g., second pad or secondoutput pad) provided in plural including a plurality of data pads DP,and an input pad IP provided in plural including a plurality of inputpads IP. The plurality of pads IP, GP and DP may include a conductivematerial. That is, the driving module DM includes the input pads IPthrough which an electrical signal is input to the driving module DMfrom outside thereof, and the gate pads GP and the data pads DP throughwhich an electrical signal is output from the driving module DM tooutside thereof (e.g., to the display panel DSP).

In embodiments, some of the input pads IP may receive electrical signalssuch as gate signals which are supplied to the pixels P and transmit thegate signals to the gate pads GP, such as by bypassing the drivingintegrated circuit DIC. Another part of the input pads IP may receiveelectrical signals such as data signals which are supplied to the pixelsP and transmit the data signals to the data pads DP through the drivingintegrated circuit DIC. Alternatively, in embodiments, a gate signal mayalso be supplied to the gate pads GP after passing through the drivingintegrated circuit DIC. In an embodiment, the gate driver may beconnected to the driving integrated circuit DIC.

The driving module DM may include a gate driving area GDA (e.g., driverarea). A driver such as gate driver may be disposed in (e.g.,corresponding to) the gate driving area GDA. That is, at least onetransistor and at least one capacitor of the gate driver may be disposedin the gate driving area GDA. Through this, an electrical signal such agate signal for driving the pixels P may be generated in the gatedriving area GDA. Electrical signals such as a start signal, a clocksignal and the like may be provided to the gate driving area GDA. A gatesignal may be provided to the pixels P by using the signals provided toand/or generated in the gate driving area GDA.

The driving module DM may include a plurality of transmissive areasincluding a first transmissive area TA1 provided in plural includingfirst transmissive areas TA1 and a second transmissive area TA2 providedin plural including second transmissive areas TA2. The firsttransmissive areas TA1 may be disposed to overlap or correspond to thecircuit film CF. An alignment mark may be provided corresponding to aplanar area where the circuit film CF overlaps the first transmissiveareas TA1 of the driving module DM. The circuit film CF may include thealignment mark. The first transmissive areas TA1 are more transparent(e.g., more light transmissive) than other planar areas of the drivingmodule DM, so that the alignment mark provided in the circuit film CFmay be recognized through the driving module DM at the firsttransmissive areas TA1 thereof. Through this, the circuit film CF andthe driving module DM may be precisely combined.

The second transmissive areas TA2 may be disposed to overlap orcorrespond to the non-display area NDA of the display panel DSP. Analignment mark may also be provided corresponding to a planar area wherethe non-display area NDA of the display panel DSP overlaps the secondtransmissive area TA2 of the driving module DM. The second transmissiveareas TA2 are more transparent (e.g., more light transmissive) thanother planar areas of the driving module DM, so that the alignment markprovided in the non-display area NDA may be recognized through thedriving module DM at the second transmissive areas TA2 thereof. Throughthis, the display panel DSP and the driving module DM may be preciselycombined.

FIG. 3 is a plan view illustrating an embodiment of a driving module DMincluded in the display device of FIG. 1. The driving module DM of FIG.3 may be substantially the same as the driving module DM of FIG. 2except that there the driving integrated circuit DIC is provided inplural including a plurality of driving integrated circuits DIC such asare two or more driving integrated circuits DIC. Therefore, adescription of the overlapping configuration will be omitted.

FIG. 4 is a cross-sectional view illustrating an embodiment taken alongthe line I-I′ of FIG. 2. Referring to FIGS. 2 and 4, the gate driver mayinclude at least one transistor and at least one capacitor. In anembodiment, for example, the gate driver may include a transistor TFT.The transistor TFT may not overlap the driving integrated circuit DICalong the third direction DR3. In an embodiment, the driving integratedcircuit DIC may be spaced apart from the transistor TFT of the gatedriver along the first direction DR1.

Referring to FIGS. 2 and 4, the driving module DM may include a firstsubstrate SUB1, buffer layer BUF, gate insulating layer GI, a firstinterlayer insulating layer ILD1, a second interlayer insulating layerILD2, a first via insulating layer VIA1, a second via insulating layerVIA2, a second substrate SUB2, a first input pad IP1, a gate pad GP, adriving integrated circuit DIC and a transistor TFT. The transistor TFTmay include an active layer ACT, a gate electrode GE, a source electrodeSE and a drain electrode DE.

The first substrate SUB1 may include a plastic material. Accordingly,the first substrate SUB1 may have a flexible characteristic such thatthe driving module DM is bendable. In an embodiment, for example, thefirst substrate SUB1 may include polyimide (“PI”). Alternatively, inembodiments, the first substrate SUB1 may include glass. Accordingly,the first substrate SUB1 may have rigid characteristics. That is, thedriving module DM may be a driving connector which connects the displaypanel DSP to the circuit film CF as the external device from whichdriving signals are provided. The circuit film CF may be a circuitboard, a circuit substrate, etc. from which the driving signals areprovided to the driving connector.

The buffer layer BUF may be disposed on the first substrate SUB1. Thebuffer layer BUF may reduce or effectively prevent diffusion of metalatoms or impurities from the first substrate SUB1 into the active layerACT. In addition, the buffer layer BUF may control a heat supply rateduring a crystallization process during providing or forming of theactive layer ACT, and accordingly, the active layer ACT may be uniformlyprovided or formed.

The active layer ACT may be disposed on the buffer layer BUF. Inembodiments, the active layer ACT may include an oxide-basedsemiconductor material. In an embodiment, for example, the oxide-basedsemiconductor material may include at least one selected from zinc oxide(“ZnOx”), tin oxide (“SnOx”), indium oxide (“InOx”), indium-zinc oxide(“IZO”), indium-gallium oxide (“IGO”), zinc-tin oxide (“ZnSnxOy”) andindium-gallium-zinc oxide (“IGZO”).

Alternatively, in embodiments, the active layer ACT may include asilicon-based semiconductor material. In an embodiment, for example, thesilicon-based semiconductor material may include at least one selectedfrom amorphous silicon, polycrystalline silicon and the like.

The gate insulating layer GI may be disposed on the buffer layer BUF tocover the active layer ACT. The gate insulating layer GI may include aninsulating material. In an embodiment, for example, the gate insulatinglayer GI may include an inorganic insulating material at least oneselected from silicon oxide (“SiOx”), silicon nitride (“SiNx”), andsilicon oxynitride (“SiNxOy”).

The gate electrode GE may be disposed on the gate insulating layer GI.The gate electrode GE may be disposed to overlap or correspond to theactive layer ACT. The gate electrode GE may include a conductivematerial. In an embodiment, for example, the gate electrode GE mayinclude at least one selected from a metal, an alloy, a conductive metaloxide, a transparent conductive material and the like. In an embodiment,for example, the gate electrode GE may include at least one selectedfrom silver (“Ag”), an alloy containing silver, molybdenum (“Mo”), analloy containing molybdenum, aluminum (“Al”), an alloy containingaluminum, aluminum nitride (“AN”), tungsten (“W”), tungsten nitride(“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride(“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), Scandium(“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”) and thelike.

The first interlayer insulating layer ILD1 may be disposed on the gateinsulating layer GI while covering the gate electrode GE. The firstinterlayer insulating layer ILD1 may include an insulating material. Inan embodiment, for example, the first interlayer insulating layer ILD1may include an inorganic insulating material. The first interlayerinsulating layer ILD1 may include at least one selected from siliconoxide (“SiOx”), silicon nitride (“SiNx”) and silicon oxynitride(“SiNxOy”).

The second interlayer insulating layer ILD2 may be disposed on the firstinterlayer insulating layer ILD1. The second interlayer insulating layerILD2 may include an insulating material. In an embodiment, for example,the second interlayer insulating layer ILD2 may include an inorganicinsulating material. The second interlayer insulating layer ILD2 mayinclude at least one selected from silicon oxide (“SiOx”), siliconnitride (“SiNx”) and silicon oxynitride (“SiNxOy”).

At least one electrode (not illustrated) may be disposed between thefirst interlayer insulating layer ILD1 and the second interlayerinsulating layer ILD2. In an embodiment, for example, a capacitanceelectrode may be disposed between the first interlayer insulating layerILD1 and the second interlayer insulating layer ILD2 along a thicknessdirection. Accordingly, an electrode (not illustrated) disposed in asame layer as the gate electrode GE may form a capacitor together withthe capacitance electrode. As being in a same layer, elements orpatterns may be respective portions of a same material layer on thefirst substrate SUB1 and/or may each extend into a same material layeron the first substrate SUB1, without being limited thereto.

The source electrode SE and the drain electrode DE may be disposed onthe second interlayer insulating layer ILD2. The source electrode SE andthe drain electrode DE may include at least one selected from a metal,an alloy, a conductive metal oxide, a transparent conductive materialand the like. Each of the source electrode SE and the drain electrode DEmay be connected to the active layer ACT at or through a contact hole.

The first via insulating layer VIA1 may cover the source electrode SEand the drain electrode DE and may be disposed on the second interlayerinsulating layer ILD2. In embodiments, the first via insulating layerVIA1 may include or be formed of an organic insulating material such aspolyimide (“PI”).

Alternatively, in embodiments, the first via insulating layer VIA1 mayinclude or be formed of an inorganic insulating material such as aninorganic insulating material of the above-described interlayerinsulating layers ILD1, ILD2 and ILD3. This may be applied equally tothe various via insulating layers described below.

The second via insulating layer VIA2 may be disposed on the first viainsulating layer VIA1. In embodiments, the second via insulating layerVIA2 may include or be formed of an organic insulating material such aspolyimide (“PI”).

The second substrate SUB2 may include a plastic material. Accordingly,the second substrate SUB2 may have a flexible characteristic. In anembodiment, for example, the second substrate SUB2 may include polyimide(“PI”). Alternatively, in embodiments, the second substrate SUB2 mayinclude glass. Accordingly, the second substrate SUB2 may have rigidcharacteristics.

The first input pad IP1 may be disposed on the second substrate SUB2.The first input pad IP1 may be a pad among the input pads IP of FIG. 2which is connected to the gate pad GP. The first input pad IP1 may beconnected to the transistor TFT. The first input pad IP1 may receive asignal from an external device (e.g., the circuit film CF of FIG. 1).The signal may include an electrical signal (e.g., input signal, drivingsignal, control signal, etc.) for driving the gate driver in the gatedriving area GDA. In an embodiment, for example, a clock signal, a startsignal or the like may be transmitted to the gate driver through thefirst input pad IP1.

The gate driver may transmit a gate signal to the gate pad GP. Throughthis, the gate signal may be transmitted to the pixels P of FIG. 1.

The driving integrated circuit DIC may be disposed on the secondsubstrate SUB2. The driving integrated circuit DIC may be connected toconnection electrodes to be described to later and fixed on the secondsubstrate SUB2. An upper surface of the second substrate SUB2 may beexposed to outside the driving module DM.

FIG. 5 is a cross-sectional view illustrating an embodiment taken alongthe line I-I′ of FIG. 2.

Referring to FIG. 5, FIG. 5 may be structurally the same as FIG. 4except that the second substrate SUB2 is excluded from FIG. 4. However,the second via insulating layer VIA2 may include an inorganic insulatingmaterial to protect the lower layers disposed under the second viainsulating layer VIA2 from external impact. In an embodiment, forexample, the second via insulating layer VIA2 may include at least oneselected from silicon oxide (“SiOx”), silicon nitride (“SiNx”), siliconoxynitride (“SiNxOy”) and the like. An upper surface of the second viainsulating layer VIA2 may be exposed to outside the driving module DM.

FIG. 6 is a cross-sectional view illustrating an embodiment taken alongthe line I-I′ of FIG. 2.

Referring to FIG. 6, the driving module DM may further include a thirdvia insulating layer VIA3 disposed on the second via insulating layerVIA2. The second via insulating layer VIA2 and the third via insulatinglayer VIA3 may include substantially the same material.

A plurality of electrodes may be disposed on the first via insulatinglayer VIA1. The plurality of electrodes connects the transistor TFT tovarious pads of the driving module DM. In embodiments, the plurality offirst connection electrodes may include a first connection electrode CE1and a second connection electrode CE2 disposed on the first viainsulating layer VIA1. The first connection electrode CE1 may connectthe first input pad IP1 and the source electrode SE to each other. Thesecond connection electrode CE2 may connect the gate pad GP and thedrain electrode DE to each other. The first connection electrode CE1 andthe second connection electrode CE2 are in a same layer as each other.

However, this is exemplary, and the pads IP and GP and the transistorTFT may be variously connected to each other by more connectionelectrodes than shown in FIG. 6. In an embodiment, for example, separateconnection electrodes may be disposed between the second via insulatinglayer VIA2 and the third via insulating layer VIA3 in addition to theplurality of electrodes may be disposed on the first via insulatinglayer VIA1.

FIG. 7 is a cross-sectional view illustrating an embodiment taken alongthe line I-I′ of FIG. 2.

Referring to FIG. 7, FIG. 7 may be structurally the same as FIG. 6except that the second substrate SUB2 is excluded from FIG. 6. However,in order to protect the lower layers from external impact, the third viainsulating layer VIA3 may include an inorganic insulating material. Inan embodiment, for example, the third via insulating layer VIA3 mayinclude any one selected from silicon oxide (“SiOx”), silicon nitride(“SiNx”) and silicon oxynitride (“SiNxOy”).

FIG. 8 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2.

Referring to FIGS. 2 and 8, the driving module DM may include a firstsubstrate SUB1, a buffer layer BUF, a gate insulating layer GI, a firstinterlayer insulating layer ILD1, a second interlayer insulating layerILD2, a first via insulating layer VIA1, a second via insulating layerVIA2, a second substrate SUB2, a third connection electrode CE3, afourth connection electrode CE4, a second input pad IP2, a drivingintegrated circuit DIC and a data pad DP. The second input pad IP2 maybe a pad among the input pads IP of FIG. 2 which is connected to thedata pad DP.

The third connection electrode CE3 and the fourth connection electrodeCE4 may be disposed on the first via insulating layer VIA1. A pluralityof first connection electrodes may include the third connectionelectrode CE3 and the fourth connection electrode CE4. The thirdconnection electrode CE3 and the fourth connection electrode CE4 are ina same layer as each other. The third connection electrode CE3 and thefourth connection electrode CE4 may include a conductive material. Thethird connection electrode CE3 may connect the second input pad IP2 andthe driving integrated circuit DIC to each other. The fourth connectionelectrode CE4 may connect the data pad DP and the driving integratedcircuit DIC to each other. Accordingly, the second input pad IP2 maytransmit a data signal transmitted from an external device (e.g., thecircuit film CF of FIG. 1) to the data pad DP, via the drivingintegrated circuit DIC.

The third connection electrode CE3 and the fourth connection electrodeCE4 may be disposed in the gate driver. In this way, the drivingintegrated circuit DIC may be connected to the gate driver through thethird connection electrode CE3 and the fourth connection electrode CE4.

FIG. 9 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2.

Referring to FIG. 9, FIG. 9 may be structurally the same as FIG. 8except that the second substrate SUB2 is excluded from FIG. 8. However,the second via insulating layer VIA2 may include an inorganic insulatingmaterial to protect the lower layers from external impact. In anembodiment, for example, the second via insulating layer VIA2 mayinclude at least one selected from silicon oxide (“SiOx”), siliconnitride (“SiNx”), silicon oxynitride (“SiNxOy”) and the like.

FIG. 10 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2. FIG. 10 may be substantially the same as FIG.8 except that the third via insulating layer VIA3, the fifth connectionelectrode CE5 and the sixth connection electrode CE6 are added.

Referring to FIG. 10, the fifth connection electrode CE5 and the sixthconnection electrode CE6 may be disposed on the second via insulatinglayer VIA2. The fifth connection electrode CE5 and the sixth connectionelectrode CE6 are in a same layer as each other. The third viainsulating layer VIA3 may be disposed to cover the fifth connectionelectrode CE5 and the sixth connection electrode CE6. The thirdconnection electrode CE3 and the fourth connection electrode CE4 mayinclude a conductive material.

The fifth connection electrode CE5 may connect the second input pad IP2and the driving integrated circuit DIC to each other. The sixthconnection electrode CE6 may connect the driving integrated circuit DICand the data pad DP to each other. Through this, the second input padIP2 may be electrically connected to the data pad DP. However, this isexemplary, and the second input pad IP2 and the data pad DP may beelectrically connected through more electrodes. In an embodiment, forexample, the second input pad IP2 and the data pad DP may beelectrically connected through connection electrodes disposed on thefirst via insulating layer VIA′.

FIG. 11 is a cross-sectional view illustrating an embodiment taken alongthe line of FIG. 2.

Referring to FIG. 11, FIG. 11 may be structurally the same as FIG. 10except that the second substrate SUB2 is excluded from FIG. 10. However,in order to protect the lower layers from external impact, the third viainsulating layer VIA3 may include an inorganic insulating material. Inan embodiment, for example, the third via insulating layer VIA3 mayinclude at least one selected from silicon oxide (“SiOx”), siliconnitride (“SiNx”) and silicon oxynitride (“SiNxOy”).

FIG. 12 is a cross-sectional view illustrating an embodiment taken alongthe line II-II′ of FIG. 2.

Referring to FIG. 12, a seventh connection electrode CE7 and an eighthconnection electrode CE8 may be disposed on the first via insulatinglayer VIA1. A ninth connection electrode CE9, a tenth connectionelectrode CE10 and an eleventh connection electrode CE11 may be disposedon the second via insulating layer VIA2. The connection electrodes CE7,CE8, CE9, CE10 and CE11 may include a conductive material. A pluralityof second connection electrodes may include more than one of the ninthconnection electrode CE9, the tenth connection electrode CE10 and theeleventh connection electrode CE11.

The ninth connection electrode CE9 may be disposed between the secondinput pad IP2 and the seventh connection electrode CE7. The ninthconnection electrode CE9 may connect the second input pad IP2 and theseventh connection electrode CE7 to each other. The seventh connectionelectrode CE7 may connect the ninth connection electrode CE9 and thedriving integrated circuit DIC to each other. The tenth connectionelectrode CE10 may be disposed between the driving integrated circuitDIC and the eighth connection electrode CE8. The tenth connectionelectrode CE10 may connect the driving integrated circuit DIC and theeighth connection electrode CE8 to each other. The eleventh connectionelectrode CE11 may be disposed between the eighth connection electrodeCE8 and the data pad DP. The eleventh connection electrode CE11 mayconnect the eighth connection electrode CE8 and the data pad DP to eachother. Through this, a signal transmitted to the second input pad IP2may be transmitted to the data pad DP through the driving integratedcircuit DIC and various connection electrodes.

FIGS. 13 to 16 are cross-sectional views illustrating embodiments of thetransmissive area of FIG. 1.

Referring to FIGS. 1, 2, 13, 14, 15, 16, the driving module DM mayinclude at least one gate insulating layer, at least one interlayerinsulating layer and at least one via insulating layer. The gateinsulating layer, the interlayer insulating layer and the via insulatinglayer may be disposed in order from the first substrate SUB1. However,the gate insulating layer, the interlayer insulating layer and the viainsulating layer may not be disposed in an area overlapping the secondtransmissive area TA2. That is, within the driving module DM, the gateinsulating layer, the interlayer insulating layer and the via insulatinglayer are excluded from or disconnected at a transmissive area of thedriving module DM. Through this, the driving module DM may secure thesecond transmissive area TA2 as a region through which light is moretransmittable (e.g., light transmissive area) than at a remaining regionof the driving module DM.

A thickness of the driving module DM and various components thereof ismay be defined along the third direction DR3, e.g., a thicknessdirection. The driving module DM may have a thickness at thetransmissive area which is less than a thickness at an area adjacent tothe transmissive area. That is, the second transmissive area TA2 of thedriving module DM is thinner than other portions of the driving moduleDM, so that the transmittance of light through the driving module DM ata respective transmissive area may be secured. FIGS. 13 to 16 illustratethe second transmissive area TA2 as a reference, however, the firsttransmissive area TA1 may have substantially the same structure.

In embodiments, the second transmissive area TA2 may be provided orformed in a planar area where the driving module DM overlaps the displaypanel DSP along the third direction DR3. That is, the secondtransmissive area TA2 may be provided formed at a first side of thedriving module DM which is closest to the display panel DSP along thefirst direction DR1. In addition, the first transmissive area TA1 may beprovided or formed in a planar area where the driving module DM overlapsthe circuit film CF along the third direction DR3. That is, the firsttransmissive area TA1 may be provided or formed at a second side whichis opposite to the first side of the driving module DM and closest tothe circuit film CF along the first direction DR1.

In embodiments, an alignment mark may be provided in an area of thedisplay panel DSP which overlaps the second transmissive area TA2 of thedriving module DM. When the driving module DM is combined with thedisplay panel DSP, the alignment mark of the display panel DSP may berecognized through the second transmissive area TA2 of the drivingmodule DM from outside thereof. That is, overlapping of the drivingmodule DM with the alignment mark disposes the alignment mark visiblefrom outside of the driving module DM at the second transmissive areaTA2 since light is transmittable through the driving module DM at thesecond transmissive area TA2 thereof.

In embodiments, an alignment mark may be provided in an area of thecircuit film CF which overlaps the first transmissive area TA1. When thedriving module DM is combined with the circuit film CF, the alignmentmark of the circuit film CF may be recognized through the firsttransmissive area TA1. That is, overlapping of the driving module DMwith the alignment mark disposes the alignment mark visible from outsideof the driving module DM at the first transmissive area TA1 since lightis transmittable through the driving module DM at the first transmissivearea TA1 thereof.

FIG. 17 is a plan view illustrating an embodiment of a display device.FIG. 17 may be substantially the same as FIG. 2 except that the drivingintegrated circuit DIC overlaps or corresponds to the gate driving areaGDA. That is, the driving integrated circuit DIC and the gate driver mayoverlap.

FIG. 18 is a cross-sectional view illustrating an embodiment taken alongline IV-IV′ of FIG. 17.

Referring to FIGS. 17 and 18, the gate driver may include at least onetransistor and at least one capacitor. In an embodiment, for example,the gate driver may include a transistor TFT. The transistor TFT mayoverlap the driving integrated circuit DIC along the third directionDR3. In this case, when electrical signals are respectively applied tothe transistor TFT and the driving integrated circuit DIC, they mayelectrically affect each other. Therefore, in order to reduce oreffectively prevent an electrical effect between the transistor TFT andthe driving integrated circuit DIC, a shielding electrode SP may bedisposed on the first via insulating layer VIA1. A constant voltage maybe applied to the shielding electrode SP. In FIG. 17, the shieldingelectrode SP is illustrated to be disposed on the first via insulatinglayer VIA1, but this is illustrative and is not limited thereto. In anembodiment, for example, the shielding electrode SP may be disposed onthe second via insulating layer VIA2 or the third via insulating layerVIA3.

FIG. 19 is a cross-sectional view illustrating an embodiment taken alongline IV-IV′ of FIG. 17. FIG. 19 may be structurally the same as FIG. 18except that the second substrate SUB2 is excluded from FIG. 18. However,in order to protect the lower layers from external impact, the third viainsulating layer VIA3 may include an inorganic insulating material. Inan embodiment, for example, the third via insulating layer VIA3 mayinclude at least one selected from silicon oxide (“SiOx”), siliconnitride (“SiNx”), and silicon oxynitride (“SiNxOy”).

FIG. 20 is a plan view illustrating an embodiment of a driving module DMincluded in the display device of FIG. 1.

Referring to FIG. 20, the driving module DM may include a first sidealong which the data pads DP and the gate pads GP are arranged, and asecond side which is opposite to the first side and closest to thecircuit film CF. A plurality of input pads IP may be arranged along thesecond side. The first side and the second side of the driving module DMare each extended along a second direction DR2. A third side and afourth side are each extended along a first direction DR1 and connectthe first side to the second side. The first side may be parallel to thesecond side, the third side may be parallel to the fourth side, and thefirst side may be perpendicular to the third side without being limitedthereto.

A groove HM provided in plural including a plurality of grooves HM maybe provided or formed along a third side and/or the fourth side.

In embodiments, providing a driving module DM may include providing aplurality of driving modules DM initially connected to each other.Thereafter, the plurality of driving modules DM may be divided toprovide individual ones of the driving module DM. In this case, theplurality of driving modules DM which are initially connected to eachother may be provided in a roll or roll type arrangement. In anembodiment of providing a driving module DM, for example, the pluralityof driving modules DM may be connected to each other, stored togetherwith each other and moved together with each other in a roll form whichis wound around a cylinder. In this case, the grooves HM may be providedor formed in the driving modules DM to easily wind the roll form of theplurality of driving modules DM around the cylinder. In an embodiment,for example, protrusions which correspond to the grooves HM may beprovided or formed in the cylinder to engage with the grooves HM.

FIG. 21 is a plan view illustrating an embodiment of a driving module DMincluded in the display device of FIG. 1.

Referring to FIGS. 2 and 21, the driving module DM may include a firstmultiplexer MX1 provided in plural including a plurality of firstmultiplexers MX1 and a second multiplexer MX2 provided in pluralincluding a plurality of second multiplexers MX2. The first multiplexersMX1 may be connected to the gate pads GP. In embodiments, each of thefirst multiplexers MX1 may be connected to the gate driver by a singleline (e.g., single signal line or conductive line). Each one of thefirst multiplexers MX1 may be connected to two of the gate pads GP bytwo lines, respectively. However, this is exemplary, and each of thefirst multiplexers MX1 may be respectively connected to three or moregate pads GP by three or more lines.

The second multiplexers MX2 may be connected to the data pads DP. Inembodiments, each of the second multiplexers MX2 may be connected to thedriving to integrated circuit DIC by a single line. One of the secondmultiplexers MX2 may be respectively connected to two data pads DP bytwo lines. However, this is exemplary, and one of the secondmultiplexers MX2 may be respectively connected to three or more datapads DP by three or more lines.

In this way, the driving module DM may include multiplexers in order toreduce the number of lines disposed in the driving module DM.

The foregoing is illustrative of the invention and is not to beconstrued as limiting thereof. Although embodiments of the inventionhave been described, those skilled in the art will readily appreciatethat many modifications are possible in the embodiments withoutmaterially departing from the novel teachings and advantages of theinvention. Accordingly, all such modifications are intended to beincluded within the scope of the invention as defined in the claims.

In the claims, means-plus-function clauses are intended to cover thestructures described herein as performing the recited function and notonly structural equivalents but also equivalent structures. Therefore,it is to be understood that the foregoing is illustrative of theinvention and is not to be construed as limited to the embodimentsdisclosed, and that modifications to the disclosed embodiments, as wellas other embodiments, are intended to be included within the scope ofthe appended claims. The invention is defined by the following claims,with equivalents of the claims to be included therein.

What is claimed is:
 1. A display device comprising: a display panel; anda driving connector connected to the display panel and from whichdriving signals are provided to the display panel, the driving connectorincluding: a driving integrated circuit, a gate pad through which afirst driving signal among the driving signals is output from thedriving connector to the display panel, a first input pad through whichthe first driving signal is input to the driving connector from outsidethereof, and a gate driver which connects the gate pad to the firstinput pad and includes: a first substrate; and a transistor on the firstsubstrate and including a source electrode connected to the first inputpad and a drain electrode connected to the gate pad, wherein within thedriving connector, the transistor and the driving integrated circuit arein order from the first substrate.
 2. The display device of claim 1,wherein the driving connector further includes: a data pad through whicha second driving signal among the driving signals is output from thedriving connector to the display panel; a second input pad through whichthe second driving signal is input to the driving connector from outsidethereof; a first connection electrode and a second connection electrodespaced apart from each other along the first substrate; and thetransistor, the first and the second connection electrodes, and thedriving integrated circuit in order from the first substrate.
 3. Thedisplay device of claim 2, wherein the first connection electrodeconnects the source electrode of the transistor and the first input padto each other, and the second connection electrode connects the drainelectrode of the transistor and the gate pad to each other.
 4. Thedisplay device of claim 2, wherein the driving connector furtherincludes: a first multiplexer connected to the data pad; and a secondmultiplexer connected to the gate pad.
 5. The display device of claim 2,wherein the first connection electrode connects the second input pad andthe driving integrated circuit to each other, and the second connectionelectrode connects the driving integrated circuit and the data pad toeach other.
 6. The display device of claim 5, wherein the drivingconnector further includes: a third connection electrode which connectsthe first connection electrode and the second input pad to each other;and a fourth connection electrode which connects the data pad and thesecond connection electrode to each other, and the transistor, the firstto fourth connection electrodes, and the driving integrated circuit inorder from the first substrate.
 7. The display device of claim 1,wherein the driving connector further includes: a data pad through whicha second driving signal among the driving signals is output from thedriving connector to the display panel; a second input pad through whichthe second driving signal is input to the driving connector from outsidethereof; and a first connection electrode and a second connectionelectrode in a same layer as the source electrode of the transistor. 8.The display device of claim 7, wherein the first connection electrodeconnects the second input pad and the driving integrated circuit to eachother, and the second connection electrode connects the drivingintegrated circuit and the data pad to each other.
 9. The display deviceof claim 1, wherein the driving connector further includes a secondsubstrate between the transistor and the first input pad and between thetransistor and the gate pad.
 10. The display device of claim 9, whereineach of the first substrate and the second substrate includes polyimide.11. The display device of claim 1, wherein the driving integratedcircuit and the gate driver overlap.
 12. The display device of claim 11,wherein the driving connector further includes a shielding electrodebetween the driving integrated circuit and the gate driver which overlapeach other.
 13. The display device of claim 1, wherein the drivingconnector further includes: a first side which is closest to the displaypanel; and at the first side, a light transmissive area through whichlight is transmittable through the driving connector.
 14. The displaydevice of claim 13, wherein the driving connector further includes: agate insulating layer, a interlayer insulating layer and a viainsulating layer in order from the first substrate to the first inputpad, and the gate insulating layer, the interlayer insulating layer andthe via insulating layer are excluded from the light transmissive area.15. The display device of claim 1, further comprising a circuit filmfrom which the driving signals are provided to the driving connector,wherein the driving connector further includes a first side which isclosest to the display panel and a second side which is opposite to thefirst side, and the circuit film is connected to the driving connectorat the second side thereof.
 16. The display device of claim 15, whereinthe driving connector further includes at the second side, a lighttransmissive area through which light is transmittable through thedriving connector.
 17. The display device of claim 16, wherein thedriving connector includes: a gate insulating layer, a interlayerinsulating layer and a via insulating layer in order from the firstsubstrate to the first input pad, and the gate insulating layer, theinterlayer insulating layer and the via insulating layer are excludedfrom the light transmissive area.
 18. The display device of claim 1,wherein the driving connector further includes the driving integratedcircuit provided in plural.
 19. The display device of claim 1, whereinthe gate driver is connected to the driving integrated circuit.
 20. Thedisplay device of claim 1, wherein the driving connector furtherincludes: a first side which is closest to the display panel, a secondside which is opposite to the first side, and a third side and a fourthside which each connect the first side to the second side, and aplurality of grooves defined along the third side and along the fourthside.